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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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CYW20733 Fiches technique(PDF) 8 Page - Cypress Semiconductor |
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CYW20733 Fiches technique(HTML) 8 Page - Cypress Semiconductor |
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8 / 67 page  Document No. 002-14859 Rev. *R Page 8 of 67 CYW20733 ■ 4 MHz maximum (Compatibility with high-speed I2C-compatible devices is not guaranteed.) The following transfer types are supported by the BSC: ■ Read (up to 127 bytes can be read) ■ Write (up to 127 bytes can be written) ■ Read-then-Write (Up to 127 bytes can be read, and up to 127 bytes can be written.) ■ Write-then-Read (Up to 127 bytes can be written, and up to 127 bytes can be read.) Hardware controls the transfers, requiring minimal firmware setup and supervision. The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20733 are required on both SCL and SDA for proper operation. 1.4.2 UART Interface The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 1.5 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI command. The CYW20733 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth 3.0 UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. The UART clock is 24 MHz. The baud rate of the CYW20733 UART is controlled by two values. The first is a UART clock divisor (also called the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (also called the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time. When setting the baud rate manually, the UART clock divisor is an 8-bit value that is stored as 256 minus the chosen divisor. For example, a divisor of 13 is stored as 256 – 13 = 243 = 0xF3. The baud rate adjustment is also an 8-bit value, of which the four MSBs are the number of additional clock cycles to insert in the first half of each bit time, and the four LSBs are the number of clock cycles to insert in the second half of each bit time. If either of these two values is over eight, it is rounded to eight. To compute the baud rate, the calculation is expressed as: 24 MHz ÷ ((16 × UART clock divisor) + total inserted 24-MHz clock cycles) Table 2 contains example values to generate common baud rates. Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW20733 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. Peripheral UART Interface The CYW20733 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each functional pin as shown in Table 3. Table 2. Common Baud Rate Examples Desired Baud Rate (bps) UART Clock Divi- sor Baud Rate Adjustment Actual Baud Rate (bps) Error (%) High Nibble Low Nibble 1500000 0xFF 0x00 0x00 1500000 0.00 921600 0xFF 0x05 0x05 923077 0.16 460800 0xFD 0x02 0x02 461538 0.16 230400 0xFA 0x04 0x04 230769 0.16 115200 0xF3 0x00 0x00 115385 0.16 57600 0xE6 0x00 0x00 57692 0.16 38400 0xD9 0x01 0x00 38400 0.00 28800 0xCC 0x00 0x00 28846 0.16 19200 0xB2 0x01 0x01 19200 0.00 14400 0x98 0x00 0x00 14423 0.16 9600 0x64 0x02 0x02 9600 0.00 |
Numéro de pièce similaire - CYW20733 |
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Description similaire - CYW20733 |
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