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BD3531F-E2 Fiches technique(PDF) 1 Page - Rohm |
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BD3531F-E2 Fiches technique(HTML) 1 Page - Rohm |
1 / 19 page ○Product structure:Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays 1/15 © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・14・001 TSZ02201-0J2J0A900950-1-2 02.Nov.2015 Rev.001 Termination Regulator for DDR-SDRAMs BD3531F General Description BD3531F is a termination regulator that complies with JEDEC requirements for DDR-SDRAM. This linear power supply uses a built-in N-channel MOSFET and high-speed OP-AMPS specially designed to provide excellent transient response. It has a sink/source current capability up to 1.5A and has a power supply bias requirement of 5.0V for driving the N-channel MOSFET. By employing an independent reference voltage input (VDDQ) and a feedback pin (VTTS), this termination regulator provides excellent output voltage accuracy and load regulation as required by JEDEC standards. Additionally, BD3531F has a reference power supply output (VREF) for DDR-SDRAM or for memory controllers. Unlike the VTT output that goes to “Hi-Z” state, the VREF output is kept unchanged when EN input is changed to “Low”, making this IC suitable for DDR- SDRAM under “Self Refresh” state. Features Incorporates a Push-Pull Power Supply for Termination (VTT) Incorporates a Reference Voltage Circuit (VREF) Incorporates an Enabler Incorporates an Undervoltage Lockout (UVLO) Incorporates a Thermal Shutdown Protector (TSD) Compatible with Dual Channel (DDR-II) Applications Power supply for DDR I/II - SDRAM Key Specifications Termination Input Voltage Range: 1.0V to 5.5V VCC Input Voltage Range: 4.5V to 5.5V Output Voltage: 1/2xVVDDQ V(Typ) Output Current: 1.5A(Max) High Side FET ON-Resistance: 0.4 Ω(Typ) Low side FET ON-Resistance: 0.4Ω(Typ) Standby Current: 0.8mA (Typ) Operating Temperature Range: -10°C to +100°C Package W(Typ) x D(Typ) x H(Max) Typical Application Circuit, Block Diagram SOP8 5.00mm x 6.20mm x 1.71mm TSD Reference Block Thermal Protection GND VREF VDDQ ½ x VTTS VTT VTT VCC VDDQ VTT_IN VCC VDDQ VTT_IN VCC UVLO 50k Ω 50k Ω VCC VCC UVLO VCC TSD EN UVLO TSD EN UVLO Enable EN Datasheet Datasheet |
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