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LM1971 Datasheet(Fiches technique) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Numéro de pièce LM1971
Description  LM1971 Overture™ Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator with/Mute
Télécharger  11 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
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 6 page
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Application Information
SERIAL DATA FORMAT
The LM1971 uses a 3-wire serial communication format that
is easily controlled by a microcontroller. The timing for the
3-wire set, comprised of DATA, CLOCK, and LOAD is shown
in
Figure 2. As depicted in Figure 2, the LOAD line is to go
low at least 150 ns before the rising edge of the first clock
pulse and is to remain low throughout the transmission of the
16 data bits. The serial data is composed of an 8-bit address,
which must always be set to 0000 0000 to select the single
audio channel, and 8 bits for attenuation setting. For both ad-
dress data and attenuation setting data, the MSB is sent first
with the address data preceding the attenuation data. Please
refer to
Figure 3 to confirm the serial data format transfer
process.
Table 1 shows the various Address and Data byte values for
different attenuation settings. Note that Address bytes other
than 0000 0000 are ignored.
µPOT SYSTEM ARCHITECTURE
The µPot’s digital interface is essentially a shift register
where serial data is shifted in, latched, and then decoded.
Once new data is shifted in, the LOAD line goes high, latch-
ing in the new data. The data is then decoded and the appro-
priate switch is activated to set the desired attenuation level.
This process is continued each and every time an attenua-
tion change is made. When the µPot is powered up, it is
placed into the Mute mode.
µPOT DIGITAL COMPATIBILITY
The µPot’s digital interface section is compatible with TTL or
CMOS logic. The shift register inputs act upon a threshold of
two diode drops above the ground level (Pin 3) or approxi-
mately 1.4V.
TABLE 1. Attenuator Register Set Description
Address Register (Byte 0)
MSB LSB
A7–A0
0000 0000
Channel 1
0000 0001
Ignored
0000 0010
Ignored
Data Register (Byte 1)
Contents
Attenuation (dB)
MSB LSB
D7–D0
0000 0000
0.0
0000 0001
1.0
0000 0010
2.0
0000 0011
3.0
:::::
::
0001 0000
16.0
0001 0001
17.0
0001 0010
18.0
0001 0011
19.0
:::::
::
0011 1101
61.0
0011 1110
62.0
0011 1111
96 (Mute)
0100 0000
96 (Mute)
:::::
::
1111 1110
96 (Mute)
1111 1111
96 (Mute)
DS012353-3
*Note: Load and clock falling edges can be coincident, however, the clock falling edge cannot be delayed more than 20 ns from the falling edge of load. It is
preferrable that the falling edge of clock occurs before the falling edge of load.
FIGURE 2. Timing Diagram
www.national.com
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