MC100LVEL34

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5

There are two distinct functional relationships between the Master Reset and Clock:

CASE 1: If the MR is deasserted (H−L), while the Clock is still high, the

outputs will follow the second ensuing clock rising edge.

CLK

Q0

Q1

Q2

EN

The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal

divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge

of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-

tionships.

Internal Clock

Disabled

Internal Clock

Enabled

MR

CLK

Q0

Q1

Q2

EN

Internal Clock

Disabled

Internal Clock

Enabled

MR

CASE 2: If the MR is deasserted (H−L), after the Clock has transitioned low, the

outputs will follow the third ensuing clock rising edge.

CASE 1

CASE 2

Figure 2. Timing Diagrams

CLOCK

OUTPUT

MR

CLOCK

OUTPUT

MR

Figure 3. Reset Recovery Time