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SLB9660XQ1.2 Fiches technique(PDF) 6 Page - Infineon Technologies AG

No de pièce SLB9660XQ1.2
Description  Trusted Platform Module
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Fabricant  INFINEON [Infineon Technologies AG]
Site Internet  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SLB9660XQ1.2 Fiches technique(HTML) 6 Page - Infineon Technologies AG

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Data Sheet
6
Revision 1.0 2014-12-12
SLB 9660 TPM1.2
Trusted Platform Module
Overview
1
Overview
The SLB 9660 is a Trusted Platform Module and is based on advanced hardware security technology. This TPM
implementation has achieved CC EAL4+ certification and serves as a basis for other TPM 1.2 products and
firmware upgrades. It is available in different packages, see Table 3-1. It supports the LPC interface and
interrupts are communicated with the serial interrupt (SERIRQ) protocol.
Features
• Compliant to TPM Main Specification, Version 1.2, Rev. 116
•LPC interface
• Approved for Google Chromebook/Chromebox
• Standard (-20..+85°C) and wide temperature range (-40..+85°C)
• TSSOP-28 and VQFN-32 package
• Optimized for battery operated devices: low standby power consumption (typ.150 µA)
• 24 PCRs
• 6 kBytes free NV memory
• Up to 10 concurrent sessions
• Up to eight 2048-bit keys can be loaded into volatile storage
• 16 slots for keys of up to 2048-bit
• 8 monotonic counters
• 1280 Bytes IO buffer
• Built-in support by Linux™ kernel version 3.10 and higher
2
LPC Interface
The SLB 9660 features the Low Pin Count (LPC) interface (for a specification, please refer to [1]). From the cycle
types defined in the mentioned specification, only the TPM-type cycles (read and write) are supported. All
accesses with different cycle types are ignored by the device.
2.1
SYNC Field Usage
Since the legacy interface is not supported anymore, the SLB 9660 will never generate SYNC ERRORs on the
LPC. It will either acknowledge a cycle with SYNC OK or use a “Long Wait” SYNC field to enlarge a cycle (that
means, inserting wait states on the bus).
2.2
Localities
The interface explicitly does not support standard IO cycles (read and write). This implies that IO-mapped
addressing of the device is not possible; only accesses via the locality-based TPM-type cycles are possible
which also means that “locality none” as defined in [4] is not supported as well.
For a detailed description of the locality addressing scheme and the registers located in each locality, please
refer to [4] as well.


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