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SLB9660VQ1.2 Fiches technique(PDF) 7 Page - Infineon Technologies AG |
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SLB9660VQ1.2 Fiches technique(HTML) 7 Page - Infineon Technologies AG |
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7 / 22 page  Data Sheet 7 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module LPC Interface 2.3 Power Management The SLB 9660 does not support the LPC power down signal (signal LPCPD) or the clock run protocol (signal CLKRUN). Power management is handled internally; no explicit power-down or standby mode is available. The device automatically enters a low-power state after each successful command/response transaction. If a transaction is started on the LPC bus from the host platform, the device will wake immediately and will return to the low-power mode after the transaction has been finished. 2.4 LPC Access Rights The registers located in the address space of the SLB 9660 are described in the respective TCG document (please refer to [4]). The registers READFIFO and WRITEFIFO mentioned in Table 2-1 below refer to the DATAFIFO register, the names are used to state whether this register is read or written. Each register has its own access rights which describe if the register is updated on a write or can be read if the associated ACTIVE.LOCALITY is set respectively not set. If the access cycle is not accepted by the TPM, it will be master aborted (no LPC SYNC cycle will be generated and no action is done on the internal registers). Table 2-1 shows which operation is done by the TPM on each register depending on the ACTIVE.LOCALITY bit. Note: In Table 2-1, “abort” means that no valid SYNC is generated when a cycle is seen by the interface which shall be aborted. The data present in an aborted write access cycle does not change the addressed register. Table 2-1 LT Register Access Matrix ACTIVE.LOCALITY set for this locality ACTIVE.LOCALITY set for different LOCALITY ACTIVE.LOCALITY not set READ WRITE READ WRITE READ WRITE STS read write abort abort abort abort INT.ENABLE read write read abort read abort INT.VECTOR read write read abort read abort INT.STATUS read reset interrupt read abort read abort INT.CAPABILITY read - (abort) read - (abort) read - (abort) ACCESS read write read write read write READFIFO read1) 1) If STS.DATA.AVAIL is not set, this access is ‘abort’. abort abort abort abort abort WRITEFIFO abort write abort abort abort abort Configuration Registers read write read abort read abort HASH.START abort write abort abort abort write2) 2) The write to HASH.START sets ACCESS.ACTIVE.LOCALITY of locality 4. HASH.DATA abort write abort abort abort abort HASH.END abort write3) 3) The write to HASH.END is an implicit release of the TPM (like a ‘1’-write to the ACCESS.ACTIVE.LOCALITY bit of locality 4). abort abort abort abort |
Numéro de pièce similaire - SLB9660VQ1.2 |
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Description similaire - SLB9660VQ1.2 |
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