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LC709203FQH-04TWG Fiches technique(PDF) 7 Page - ON Semiconductor |
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LC709203FQH-04TWG Fiches technique(HTML) 7 Page - ON Semiconductor |
7 / 22 page LC709203F www.onsemi.com 7 Table 5. I 2C Slave Characteristics at Ta = 40 to +85C, VSS = 0V Parameter Symbol Pin/Remarks Conditions Specification unit VDD [V] min Max Clock frequency TSCL SCL 2.5 to 4.5 400 kHz Bus free time between STOP condition and START condition TBUF SCL, SDA See Fig. 5. 1.3 s Hold time (repeated) START condition First clock pulse is generated after this interval THD:STA SCL, SDA See Fig. 5. 0.6 s Repeated START condition setup time TSU:STA SCL, SDA See Fig. 5. 0.6 s STOP condition setup time TSU:STO SCL, SDA See Fig. 5. 0.6 s Data hold time THD:DAT SCL, SDA See Fig. 5. 0 0.9 s Data setup time TSU:DAT SCL, SDA See Fig. 5. 100 ns Clock low period TLOW SCL See Fig. 5. 1.3 s Clock high period THIGH SCL See Fig. 5. 0.6 s Clock/data fall time TF SCL, SDA 20 + 0.1CB 300 ns Clock/data rise time TR SCL, SDA 20 + 0.1CB 300 ns Wake up time from Sleep mode TWU SDA See Fig. 6. 400 s SDA low pulse width to wake up TSP SDA See Fig. 6. 0.6 s Wake up retention time from the falling edge of SDA TWR1 SDA See Fig. 6. 500 ms Wake up retention time from STOP condition TWR2 SCL, SDA See Fig. 6. 500 ms SCL SDA Figure 5. I2C Timing Diagram t HD:STA t SU:STO tBUF t LOW t HD:DAT t HIGH t R t F t SU:DAT t SU:STA t HD:STA PS S P |
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