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TPS2214 Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS2214 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 29 page www.ti.com TPS2220A, TPS2223A TPS2224A, TPS2226A SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004 PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC) RESET = 5.5 V -1 1 II(/RESET) (5) RESET = 0 V -30 -20 -10 SHDN = 5.5 V -1 1 II(/SHDN)(5) II Input current, logic SHDN = 0 V -50 -3 µA LATCH = 5.5 V 50 II(LATCH)(5) LATCH = 0 V -1 1 II(CLOCK, DATA) 0 V to 5.5 V -1 1 VIH High-level input voltage, logic 2 V VIL Low-level input voltage, logic 0.8 V VO(sat) Output saturation voltage at OC IO = 2 mA 0.14 0.4 V Ilkg Leakage current at OC VO(/OC) = 5.5 V 0 1 µA UVLO AND POR (POWER-ON RESET) VI(3.3V) Input voltage at 3.3V pin, UVLO 3.3-V level below which all switches are Hi-Z 2.4 2.7 2.9 V Vhys(3.3V) UVLO hysteresis voltage at VA(6) 100 mV VI(5V) Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z 2.3 2.5 V Delay from voltage hit (step from 3 V to 2.3 V) to Vhys(5V) UVLO hysteresis voltage at 5V(6) 100 mV Hi-Z control (90% VG to GND) tdf Delay time for falling response, UVLO(6) 4 µs 3.3-V voltage below which POR is asserted causing a VI(POR) Input voltage, power-on reset(6) RESET internally with all line switches open and all 1.7 V discharge switches closed. (5) LATCH has low-current pulldown. RESET and SHDN have low-current pullup. (6) Specified by design; not tested in production. 5 |
Numéro de pièce similaire - TPS2214 |
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Description similaire - TPS2214 |
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