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SI9181DQ-20-T1-E3 Fiches technique(PDF) 4 Page - Vishay Siliconix |
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SI9181DQ-20-T1-E3 Fiches technique(HTML) 4 Page - Vishay Siliconix |
4 / 10 page Si9181 Vishay Siliconix www.vishay.com 4 Document Number: 71119 S-40694—Rev. D, 19-Apr-04 TIMING WAVEFORMS VIN 0.95 VNOM VOUT VOUT ERROR VNOM tDELAY FIGURE 4. Timing Diagram for Power-Up tON PIN CONFIGURATION 5 CNOISE SD GND SENSE or ADJ VIN VOUT TSSOP-8 6 7 8 2 3 4 1 Top View DELAY ERROR PIN DESCRIPTION Pin Number Name Function 1 CNOISE Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected from this pin to ground. 2 DELAY Capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (Pin 7) output. Refer to Figure 4. 3 GND Ground pin. Local ground for CNOISE and COUT. 4 VIN Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground. 5 VOUT Output voltage. Connect COUT between this pin and ground. 6 SENSE or ADJ For fixed output voltage versions, this pin should be connected to VOUT (Pin 5). For adjustable output voltage version, this voltage feedback pin sets the output voltage via an external resistor divider. 7 ERROR This open drain output is an error flag output which goes low when VOUT drops 5% below its nominal voltage. This pin also provides a power-on-reset signal if a capacitor is connected to the DELAY pin. 8 SD By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused. |
Numéro de pièce similaire - SI9181DQ-20-T1-E3 |
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Description similaire - SI9181DQ-20-T1-E3 |
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