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SI5347 Fiches technique(PDF) 11 Page - Silicon Laboratories |
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SI5347 Fiches technique(HTML) 11 Page - Silicon Laboratories |
11 / 55 page 3.7 Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3) are monitored for LOS and OOF, as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs also has an LOL indica- tor, which is asserted when synchronization is lost with their selected input clock. Si5347 IN3 IN3b XB XA OSC LOS DSPLL A PD LPF ÷M LOL DSPLL B PD LPF ÷M LOL DSPLL C PD LPF ÷M LOL DSPLL D PD LPF ÷M LOL IN1 IN1b IN2 IN2b IN0 IN0b Precision Fast OOF LOS Precision Fast OOF LOS Precision Fast OOF LOS Precision Fast OOF LOS ÷ P0n P0d ÷ P1n P1d ÷ P2n P2d ÷ P3n P3d Figure 3.7. Si5347 Fault Monitors 3.7.1 Input LOS Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. LOS en Monitor LOS LOS Sticky Live Figure 3.8. LOS Status Indicators 3.7.2 XA/XB LOS Detection A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected. Si5347/46 Rev D Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 10 |
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