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M38B57MC Fiches technique(PDF) 31 Page - Mitsubishi Electric Semiconductor |
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M38B57MC Fiches technique(HTML) 31 Page - Mitsubishi Electric Semiconductor |
31 / 69 page MITSUBISHI MICROCOMPUTERS 38B5 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 31 PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. 4. SRDY1 output signal The SRDY1 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. In the initial status, when the serial I/O initialization bit (b4) is reset to “0,” ________ the SRDY1 output goes to “L” and the SRDY1 output goes to “H”. After transmitted data is stored in the serial I/O1 register (address 001B16) and a transmit/receive operation becomes ready, the SRDY1 output ________ goes to “H” and the SRDY1 output goes to “L”. When a transmit/ receive operation is started and the transfer clock goes to “L”, the ________ SRDY1 output goes to “L” and the SRDY1 output goes to “H”. 5. SRDY1 input signal The SRDY1 input signal becomes valid only when the SRDY1 input and the SBUSY1 output are used. The SRDY1 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. When the internal synchronous clock is selected, input a low level _________ signal into the SRDY1 input and a high level signal into the SRDY1 input in the initial status in which the transfer is stopped. When an “H” level signal is input into the SRDY1 input and an “L” _________ level signal is input into the SRDY1 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK1 output and a transmit/receive operation is started. After the transmit/receive operation is started and an “L” level sig- nal is input into the SRDY1 input and an “H” level signal into the _________ SRDY1 input, this operation cannot be immediately stopped. After the specified number of bits are transmitted and received, the transfer clocks from the SCLK1 output is stopped. The handshake unit of the 8-bit serial I/O and that of the automatic transfer serial I/O are of 8 bits. When the external synchronous clock is selected, the SRDY1 input becomes one of the triggers to output the SBUSY1 signal. _________ To start a transmit/receive operation (SBUSY1 output: “L,” SBUSY1 output: “H”), input an “H” level signal into the SRDY1 input and an “L” _________ level signal into the SRDY1 input, and also write transmit data into the serial I/O1 register. Fig. 30 SRDY1 Output Operation Fig. 31 SRDY1 Input Operation (internal synchronous clock) SRDY1 SCLK1 Write to serial I/O1 register SRDY1 SCLK1 SOUT1 |
Numéro de pièce similaire - M38B57MC |
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Description similaire - M38B57MC |
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