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M38B57MC Fiches technique(PDF) 51 Page - Mitsubishi Electric Semiconductor |
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M38B57MC Fiches technique(HTML) 51 Page - Mitsubishi Electric Semiconductor |
51 / 69 page MITSUBISHI MICROCOMPUTERS 38B5 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 51 PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Interrupt Interval Determination Function The 38B5 group has an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter. Using this counter, it determines a duration of time from the rising edge (falling edge) of an input signal pulse on the P47/INT2 pin to the rising edge (falling edge) of the signal pulse that is input next. How to determine the interrupt interval is described below. 1. Enable the INT2 interrupt by setting bit 2 of the interrupt control register 1 (address 003E16). Select the rising interval or falling interval by setting bit 2 of the interrupt edge selection register (address 003A16). 2. Set bit 0 of the interrupt interval determination control register (address 003116) to “1” (interrupt interval determination operat- ing). 3. Select the sampling clock of 8-bit binary up counter by setting bit 1 of the interrupt interval determination control register. When writing “0,” f(XIN)/128 is selected (the sampling interval: 32 µs at f(XIN) = 4.19 MHz); when “1,” f(XIN)/256 is selected (the sampling interval: 64 µs at f(XIN) = 4.19 MHz). 4. When the signal of polarity which is set on the INT2 pin (rising or falling edge) is input, the 8-bit binary up counter starts count- ing up of the selected counter sampling clock. 5. When the signal of polarity above 4 is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 003016), and the remote control interrupt request occurs. Immediately after that, the 8-bit binary up counter continues to count up again from “0016.” 6. When count value reaches “FF16,” the 8-bit binary up counter stops counting up. Then, simultaneously when the next counter sam- pling clock is input, the counter sets value “FF16” to the interrupt interval determination register to generate the counter overflow interrupt request. Fig. 57 Interrupt Interval Determination Circuit Block Diagram Noise filter The P47/INT2 pin builds in the noise filter. The noise filter operation is described below. 1. Select the sampling clock of the input signal with bits 2 and 3 of the interrupt interval determination control register. When not using the noise filter, set “00.” 2. The P47/INT2 input signal is sampled in synchronization with the selected clock. When sampling the same level signal in a series of three sampling, the signal is recognized as the interrupt signal, and the interrupt request occurs. When setting bit 4 of interrupt interval determination control register to “1,” the interrupt request can occur at both rising and falling edges. When using the noise filter, set the minimum pulse width of the INT2 input signal to 3 cycles or more of the sample clock. Note: In the low-speed mode (CM7 = 1), the interrupt interval deter- mination function cannot operate. f(XIN)/128 f(XIN)/256 1/128 1/64 1/32 f(XIN) Counter sampling clock selection bit INT2 interrupt input Noise filter 8-bit binary up counter Interrupt interval determination register address 003016 Data bus Divider One-sided/both-sided detection selection bit Noise filter sampling clock selection bit Counter overflow interrupt request or remote control interrupt request |
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