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M38B57MC Fiches technique(PDF) 46 Page - Mitsubishi Electric Semiconductor |
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M38B57MC Fiches technique(HTML) 46 Page - Mitsubishi Electric Semiconductor |
46 / 69 page MITSUBISHI MICROCOMPUTERS 38B5 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 46 PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 50 Structure of P8FLD Output Control Register Fig. 49 FLDC Timing P8FLD output control register (P8FLDCON: address 0EFC16) P84–P87 FLD output reverse bits 0: Output normally 1: Reverse output Not available (returns “0” when read) b7 b0 Toff1 Tdisp Segment Digit Segment Digit output Segment setting by software FLD blanking interrupt request occurs at the falling edge of the last timing. FLD digit interrupt request occurs at the rising edge of digit (each timing). Tdisp Tscan Repeat synchronous Tn Tn-1 Tn-2 T4 T3 T2 T1 Toff1 Toff2 Segment Digit When a gradation display mode is selected Pin under the condition that bit 5 of the FLDC mode register is “1,” and the corresponding gradation display control data value is “1.” Tdisp n: Number of timing |
Numéro de pièce similaire - M38B57MC |
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Description similaire - M38B57MC |
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