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M38B57MC Fiches technique(PDF) 35 Page - Mitsubishi Electric Semiconductor |
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M38B57MC Fiches technique(HTML) 35 Page - Mitsubishi Electric Semiconductor |
35 / 69 page MITSUBISHI MICROCOMPUTERS 38B5 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 35 PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. [Serial I/O2 Control Register] SIO2CON (001D16) The serial I/O2 control register contains eight control bits for serial I/O2 functions. [UART Control Register] UARTCON (001716) This is a 5 bit register containing four control bits (b0 to b3), which are valid when UART is selected and set the data format of data receive/transfer, and one control bit (b4), which is always valid and sets the output structure of the P55/TxD pin. [Serial I/O2 Status Register] SIO2STS (001E16) The read-only serial I/O2 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial I/O2 function and various errors. Three of the flags (b4 to b6) are only valid in the UART mode. The receive buffer full flag (b1) is cleared to “0” when the receive buffer is read. The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A writing to the serial I/O2 status regis- ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing “0” to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2 control register) also clears all the status flags, including the error flags. All bits of the serial I/O2 status register are initialized to “0” at reset, but if the transmit enable bit (b4) of the serial I/O2 control register has been set to “1,” the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become “1.” [Serial I/O2 Transmit Buffer Register/Receive Buffer Register] TB/RB (001F16) The transmit buffer and the receive buffer are located in the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator] BRG (001616) The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register, the baud rate genera- tor divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. Fig. 38 Structure of Serial I/O2 Related Register b7 b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) Serial I/O2 status register (SIO2STS : address 001E16) Serial I/O2 control register (SIO2CON : address 001D16) b0 b0 b7 UART control register (UARTCON : address 001716) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P55/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) BRG clock switch bit 0: XIN or XCIN (depends on internal system clock) 1: XCIN Serial I/O2 clock I/O pin selection bit 0: SCLK21 (P57/SCLK22 pin is used as I/O port or SRDY2 output pin.) 1: SCLK22 (P56/SCLK21 pin is used as I/O port.) Not used (return "1" when read) b0 BRG count source selection bit (CSS) 0: f(XIN) or f(XCIN)/2 or f(XCIN) 1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4 Serial I/O2 synchronous clock selection bit (SCS) 0: BRG/ 4 (when clock synchronous serial I/O is selected) BRG/16 (UART is selected) 1: External clock input (when clock synchronous serial I/O is selected) External clock input/16 (UART is selected) SRDY2 output enable bit (SRDY) 0: P57 pin operates as ordinary I/O pin 1: P57 pin operates as SRDY2 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O2 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O2 enable bit (SIOE) 0: Serial I/O2 disabled (pins P54 to P57 operate as ordinary I/O pins) 1: Serial I/O2 enabled (pins P54 to P57 operate as serial I/O pins) |
Numéro de pièce similaire - M38B57MC |
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Description similaire - M38B57MC |
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