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M38B57MC Fiches technique(PDF) 33 Page - Mitsubishi Electric Semiconductor |
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M38B57MC Fiches technique(HTML) 33 Page - Mitsubishi Electric Semiconductor |
33 / 69 page MITSUBISHI MICROCOMPUTERS 38B5 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 33 PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. qSerial I/O2 Serial I/O2 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during serial I/O2 operation. (1) Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode can be selected by setting the serial I/O2 mode selection bit (b6) of the serial I/O2 control reg- Fig. 35 Operation of Clock Synchronous Serial I/O2 Function Fig. 34 Block Diagram of Clock Synchronous Serial I/O2 ister (address 001D16) to “1.” For clock synchronous serial I/O, the transmitter and the receiver must use the same clock for serial I/O2 operation. If an internal clock is used, transmit/receive is started by a write signal to the serial I/O2 transmit/receive buffer register (TB/ RB) (address 001F16). _________ When P57 (SCLK22) is selected as a clock I/O pin, SRDY2 output function is invalid, and P56 (SCLK21) is used as an I/O port. 1/4 1/4 F/F P56/SCLK21 P54/RXD P55/TXD P57/SRDY2/SCLK22 “0” “1” “0” “1” XIN 1/2 XCIN “1” “0” P57/SRDY2/SCLK22 Serial I/O2 status register Serial I/O2 control register Receive buffer register Address 001F16 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit Shift clock Serial I/O2 synchronous clock selection bit Baud rate generator Division ratio 1/(n+1) Address 001616 BRG count source selection bit Clock control circuit Falling edge detector Transmit buffer register Data bus Address 001F16 Shift clock Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001E16 Data bus Address 001D16 Transmit shift register Serial I/O2 clock I/O pin selection bit Internal system clock selection bit BRG clock switch bit Serial I/O2 clock I/O pin selection bit D7 D7 D0 D1 D2 D3 D4 D5 D6 D0 D1 D2 D3 D4 D5 D6 RBF = 1 TSC = 1 TBE = 0 TBE = 1 TSC = 0 Transmit/Receive shift clock (1/2—1/2048 of internal clock or external clock) Serial I/O2 output TxD Serial I/O2 input RxD Write-in signal to serial I/O2 transmit/receive buffer register (address 001F16) Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1.” Receive enable signal SRDY2 |
Numéro de pièce similaire - M38B57MC |
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Description similaire - M38B57MC |
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