TDA8359J datasheet(6/20 Pages) PHILIPS

No de pièce	TDA8359J

Description	Full bridge vertical deflection output circuit in LVDMOS

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Fabricant	PHILIPS [NXP Semiconductors]

Site Internet	http://www.nxp.com

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6 / 20 page

2002 Jan 21

6

Philips Semiconductors

Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS

TDA8359J

CHARACTERISTICS

VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb =25 °C; measured in test circuit of Fig.3; unless otherwise

speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

VP

operating supply voltage

7.5

12

18

V

VFB

ﬂyback supply voltage

note 1

2

× V

P

45

66

V

Iq(P)(av)

average quiescent supply current

during scan

−

10

15

mA

Iq(P)

quiescent supply current

no signal; no load

−

45

75

mA

Iq(FB)(av)

average quiescent ﬂyback supply

current

during scan

−−

10

mA

Inputs A and B

Vi(p-p)

input voltage (peak-to-peak value)

note 2

−

1000

1500

mV

VI(bias)

input bias voltage

note 2

100

880

1600

mV

II(bias)

input bias current

source

−

25

35

µA

Outputs A and B

Vloss(1)

voltage loss ﬁrst scan part

note 3

Io = 1.1 A

−−

4.5

V

Io = 1.6 A

−−

6.6

V

Vloss(2)

voltage loss second scan part

note 4

Io = −1.1 A

−−

3.3

V

Io = −1.6 A

−−

4.8

V

Io(p-p)

output current

(peak-to-peak value)

−−

3.2

A

LE

linearity error

Io(p-p) = 3.2 A; notes 5 and 6

adjacent blocks

−

12%

non adjacent blocks

−

13%

Voffset

offset voltage

across RM; Vi(dif) =0V

VI(bias) = 200 mV

−−±15

mV

VI(bias) =1V

−−±20

mV

∆V

offset(T)

offset voltage variation with

temperature

across RM; Vi(dif) =0V

−−

40

µV/K

VO

DC output voltage

Vi(dif) =0V

−

0.5

× VP −

V

Gv(ol)

open-loop voltage gain

notes 7 and 8

−

60

−

dB

f− 3dB(h)

high

−3 dB cut-off frequency

open-loop

−

1

−

kHz

Gv

voltage gain

note 9

−

1

−

∆G

v(T)

voltage gain variation with the

temperature

−−

10−4

K−1

PSRR

power supply rejection ratio

note 10

80

90

−

dB

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