Moteur de recherche de fiches techniques de composants électroniques |
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DS90C363A Fiches technique(PDF) 4 Page - National Semiconductor (TI) |
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DS90C363A Fiches technique(HTML) 4 Page - National Semiconductor (TI) |
4 / 10 page AC Timing Diagrams Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 10: Recommended pin to signal mapping. Customer may choose to define differently. DS100138-4 FIGURE 1. “Worst Case” Test Pattern DS100138-5 FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10) DS100138-30 FIGURE 3. DS90C363A/DS90CF363A (Transmitter) LVDS Output Load www.national.com 4 |
Numéro de pièce similaire - DS90C363A |
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Description similaire - DS90C363A |
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