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M38867M8A Fiches technique(PDF) 47 Page - Mitsubishi Electric Semiconductor |
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M38867M8A Fiches technique(HTML) 47 Page - Mitsubishi Electric Semiconductor |
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47 / 110 page  47 3886 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [I2C START/STOP Condition Control Register (S2D)] 001716 The I2C START/STOP condition control register (address 001716) controls START/STOP condition detection. •Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(XIN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 13. Do not set “000002” or an odd number to the START/STOP condi- tion set bit (SSC4 to SSC0). Refer to Table 14, the recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency. •Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin. •Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. Note: When changing the setting of the SCL/SDA interrupt pin polarity se- lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the inter- rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt. •Bit 7: START/STOP condition generating selection bit (STSPSEL) Setup/Hold time when the START/STOP condition is generated can be selected. Cycle number of system clock becomes standard for setup/hold time. Additionally, setup/hold time is different between the START condition and the STP condition. (Refer to Tables 11 and 12.) Set “1” to this bit when the system clock frequency is 4 MHz or more. Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 001516) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 001316). At the time of this comparison, address com- parison of the RBW bit of the I2C address register (address 001316) is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 46, (1) and (2). 10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 001516) to “1.” An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C address register (address 001316). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address 001316) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RBW bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is pro- cessed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (address 001416) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 001216), perform an address com- parison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RBW bit of the I2C address register (address 001316) to “1” by software. This processing can make the 7-bit slave address and R/W data agree, which are re- ceived after a RESTART condition is detected, with the value of the I2C address register (address 001316). For the data trans- mission format when the 10-bit addressing format is selected, refer to Figure 46, (3) and (4). |
Numéro de pièce similaire - M38867M8A |
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Description similaire - M38867M8A |
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