Rev: 1.02 9/2002

9/26

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88018/32/36AT-250/225/200/166/150/133

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CR

CW

X

X

WR

R

WR

X

X

X

CR

R

CW

CR

CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.