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A1356 Fiches technique(PDF) 8 Page - Allegro MicroSystems |
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A1356 Fiches technique(HTML) 8 Page - Allegro MicroSystems |
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8 / 20 page  High Precision Linear Hall-Effect Sensor IC With an Open Drain Pulse Width Modulated Output A1356 8 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Characteristic Definitions Power-On Time When the supply is ramped to its operating voltage, the device requires a finite time to power its internal components before supplying a valid PWM output duty-cycle. Power-On Time, tPO, is defined as the time it takes for the output voltage to settle within ±10% of its steady state value after the power supply has reached its minimum specified operating volt- age, VCC(min). (See figure 1.) Propagation Delay Traveling time of signal from input Hall plate to output stage of device. (See figure 2.) Response Time The time interval between a) when the applied magnetic field reaches 90% of its final value, and b) when the sensor IC reaches 90% of its output corresponding to the applied magnetic field. (See figure 2.) PWM Rise Time The time elapsed between 10% and 90% of the rising signal value when output switches from low to high states. PWM Fall Time The time elapsed between 90% and 10% of the falling signal value when output switches from high to low states. Quiescent Duty Cycle In the quiescent state (no significant magnetic field: B = 0 G), the output duty cycle, D(Q), equals a specific programmed duty cycle throughout the entire operating ranges of VCC and ambient temperature, TA. Guaranteed Quiescent Duty Cycle Output Range The Quiescent Duty Cycle Output, D(Q), can be programmed around its nominal value of 50% D, within the Guaranteed Quiescent Duty Cycle Range limits: D(Q)(min) and D(Q)(max). The available guaranteed programming range for D(Q) falls within the distribu- tions of the minimum and the maximum programming code for setting D(Q). (See figure 3.) Average Quiescent Duty Cycle Output Step Size The average quiescent duty cycle output step size for a single device is determined using the following calculation: D(Q)(max) – D(Q)(min) 2n –1 StepD(Q) = , (1) where: n is the number of available programming bits in the trim range, 2n–1 is the value of programming steps in the range, D(Q)(max) is the maximum reached quiescent duty cycle, and D(Q)(min) is minimum reached quiescent duty cycle. Figure 1. Definition of Power-On Time Figure 2. Definitions of Propagation Delay and Response Time Figure 3. Definition of Guaranteed Quiescent Voltage Output Range Guaranteed D(Q) Programming Range D(Q)(min) D(Q)(max) Max Code D(Q) Distribution Min Code D(Q) Distribution Initial D(Q) Distribution Propagation Delay 0.5 ms Output Time Applied Magnetic Field, B Response Time Time V+ VCC(min) tPO First valid duty cycle VCC A1356 Output |
Numéro de pièce similaire - A1356_16 |
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Description similaire - A1356_16 |
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