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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TDA8024T Fiches technique(PDF) 11 Page - NXP Semiconductors |
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TDA8024T Fiches technique(HTML) 11 Page - NXP Semiconductors |
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11 / 29 page  2004 July 12 11 Philips Semiconductors Product specification IC card interface TDA8024 8.5 Inactive mode After a Power-on reset, the circuit enters the inactive mode. A minimum number of circuits are active while waiting for the microcontroller to start a session: • All card contacts are inactive (approximately 200 Ω to GND) • Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 k Ω pull-up resistor to VDD) • Voltage generators are stopped • XTAL oscillator is running • Voltage supervisor is active • The internal oscillator is running at its low frequency. 8.6 Activation sequence After power-on and after the internal pulse width delay, the system microcontroller can check the presence of a card using the signals OFF and CMDVCC as shown in Table 2. Table 2 Card presence indication If the card is in the reader (this is the case if PRES or PRES is active), the system microcontroller can start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Fig.6): 1. CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t0). 2. The voltage doubler is started (between t0 and t1). 3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t2 =t1 + 1.5 × T) where T is 64 times the period of the internal oscillator (approximately 25 µs). 4. I/O, AUX1 and AUX2 are enabled (t3 =t1 + 4T) (these were pulled LOW until this moment). 5. CLK is applied to the C3 contact of the card reader (t4). 6. RST is enabled (t5 =t1 + 7T). The clock may be applied to the card using the following sequence: 1. Set RSTIN HIGH. 2. Set CMDVCC LOW. 3. Reset RSTIN LOW between t3 and t5; CLK will start at this moment. 4. RST remains LOW until t5, when RST is enabled to be the copy of RSTIN. 5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK pulses before toggling RST. If the applied clock is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this case, CLK will start at t3 (minimum 200 ns after the transition on I/O), and after t5, RSTIN may be set HIGH in order to obtain an Answer To Request (ATR) from the card. Activation should not be performed with RSTIN held permanently HIGH. 0 (2) (1) 6 4 2 0 20 40 t (ns) Vo (V) 12 8 4 0 Io (mA) 60 FCE661 Fig.6 I/O, AUX1 and AUX2 output voltage and current as functions of time during a LOW-to-HIGH transition. (1) Current. (2) Voltage. OFF CMDVCC INDICATION HIGH HIGH card present LOW HIGH card not present |
Numéro de pièce similaire - TDA8024T |
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Description similaire - TDA8024T |
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