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UC2848 Fiches technique(PDF) 4 Page - Texas Instruments

No de pièce UC2848
Description  Average Current Mode PWM Controller
Download  13 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

UC2848 Fiches technique(HTML) 4 Page - Texas Instruments

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4
UC1848
UC2848
UC3848
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range
of
−55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC
= 12V, CT = 400pF, CI = 100pF, IOFF = 100
µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA =TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UV Comparator
Turn-on Threshold
4.1
4.35
4.6
V
RHYSTERESIS
Vuv = 4.2V
77
90
103
k
Reference
VREF
TA = 25°C
4.95
5
5.05
V
0
< IO < 10mA, 12 < VCC < 20
4.93
5.07
V
Line Regulation
12 < VCC < 20V
4
15
mV
Load Regulation
0 < IO < 10mA
3
15
mV
Short Circuit Current
VREF = 0V
30
50
70
mA
Output Stage
Rise & Fall Time (Note 1)
Cl = 1nF
20
45
ns
Output Low Saturation
IO = 20mA
0.25
0.4
V
IO = 200mA
1.2
2.2
V
Output High Saturation
IO = -200mA
2.0
3.0
V
UVLO Output Low Saturation
IO = 20mA
0.8
1.2
V
ICC
ISTART
VCC = 12V
0.2
0.4
mA
ICC (pre-start)
VCC = 15V, V(UV) = 0
0.5
1
mA
ICC (run)
22
26
mA
Under Voltage Lockout
The Under Voltage Lockout block diagram is shown in
Fig 1. The VCC comparator monitors chip supply voltage.
Hysteretic thresholds are set at 13V and 10V to facilitate
off-line applications. If the VCC comparator is low, ICC is
low (<500
µA) and the output is low.
The UV comparator monitors input line voltage (VIN). A
pair of resistors divides the input line to UV. Hysteretic in-
put line thresholds are programmed by Rv1 and Rv2. The
thresholds are
VIN(on) = 4.35V • (1 + Rv1/Rv2′) and
VIN(off) = 4.35V • (1 + Rv1/Rv2) where
Rv2
′= Rv2||90k.
The resulting hysteresis is
VIN(hys) = 4.35V • Rv1 / 90k.
When the UV comparator is low, ICC is low (500µA) and
the output is low.
When both the UV and VCC comparators are high, the
internal bias circuitry for the rest of the chip is activated.
The CDC pin (see discussion on Maximum Duty Cycle
Control and Soft Start) and the Output are held low until
VREF exceeds the 4.5V threshold of the VREF compara-
tor. When VREF is good, control of the output driver is
transferred to the PWM circuitry and CDC is allowed to
charge.
If any of the three UVLO comparators go low, the UVLO
latch is set, the output is held low, and CDC is dis-
charged. This state will be maintained until all three com-
parators are high and the CDC pin is fully discharged.
APPLICATION INFORMATION


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