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UC1848 Fiches technique(PDF) 8 Page - Texas Instruments |
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UC1848 Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 13 page 8 UC1848 UC2848 UC3848 UDG-93012-1 UDG-93013-1 Maximum Volt-Second Circuit A maximum volt-second product can be programmed by a resistor (Rvs) from VS to VIN and a capacitor (Cvs) from VS to ground (Figure 7). VS is discharged while the switch is off. When the output turns on, VS is allowed to charge. Since the threshold of the VS comparator is much less than VIN, the charging profile at Vs will be es- sentially linear. If VS crosses the 4.0V threshold before the PWM turns the output off, the VS comparator will turn the output off for the remainder of the cycle. The maxi- mum volt-second product is VIN • TON(max) = 4.0V • Rvs • Cvs. Maximum Duty Cycle And Soft Start A patented technique is used to accurately program max- imum duty cycle. Programming is accomplished by a di- vider from VREF to DMAX (Fig. 7). The value programmed is: D(max) = Rd1 / (Rd1 + Rd2). For proper operation, the integrating capacitor, CDC, should be larger than CDC(min) >T(osc) / 80k, where T(osc) is the oscillator period. CDC also sets the soft start time constant, so values of CDC larger than minimum may be desired. The soft start time constant is approximately: T(ss) = 20k • CDC. Ground Planes The output driver on the UC3848 is capable of 2A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed (Fig. 8). A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. This point is the power ground to which to PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, al- though this is not strictly necessary if the high di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high fre- quency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection for input power to the system and the bulk in- put capacitor. The output should be clamped with a high current Schottky diode to both VCC and PGND. Nothing else should be connected to power ground. VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low esr/esl ceramic 1 F capacitors are recommended for both VCC and VREF. The capacitors from CT, CDC, and CI should likewise be connected to the signal ground plane. APPLICATION INFORMATION (cont.) |
Numéro de pièce similaire - UC1848_14 |
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Description similaire - UC1848_14 |
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