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ST16C2450CJ44 Fiches technique(PDF) 9 Page - Exar Corporation

No de pièce ST16C2450CJ44
Description  2.97V TO 5.5V DUART
Download  29 Pages
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Fabricant  EXAR [Exar Corporation]
Site Internet  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C2450CJ44 Fiches technique(HTML) 9 Page - Exar Corporation

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ST16C2450
REV. 4.0.0
2.97V TO 5.5V DUART
9
2.8
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 1 byte FIFO or Transmit
Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods.
The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled,
and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5
and bit-6).
2.8.1
Transmit Holding Register (THR) - Write Only
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00
0
2400
384
180
01
80
0
4800
192
C0
00
C0
0
9600
96
60
00
60
0
19.2k
483000
30
0
38.4k
241800
18
0
76.8k
12
0C
00
0C
0
153.6k
6
06
00
06
0
230.4k
4
04
00
04
0
460.8k
2
02
00
02
0
921.6k
1
01
00
01
0
FIGURE 5. TRANSMITTER OPERATION
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock


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