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ST16C2450 Fiches technique(PDF) 6 Page - Exar Corporation |
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ST16C2450 Fiches technique(HTML) 6 Page - Exar Corporation |
6 / 29 page ST16C2450 áç áç áç áç 2.97V TO 5.5V DUART REV. 4.0.0 6 1.0 PRODUCT DESCRIPTION The ST16C2450 (2450) integrates the functions of two 16C450 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The 2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to- parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The 2450 represents such an integration with greatly enhanced features. The 2450 is fabricated with an advanced CMOS process. The 2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a crystal or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps. 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2450 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share the same data bus for host operations. The data bus interconnections are shown in Figure 3. . 2.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 8). An active high pulse of at least 40 ns duration will be required to activate the reset function in the device. FIGURE 3. ST16C2450 DATA BUS INTERCONNECTIONS VCC VCC OP2A# DSRA# CTSA# RTSA# DTRA# RXA TXA RIA# CDA# OP2B# DSRB# CTSB# RTSB# DTRB# RXB TXB RIB# CDB# GND A0 A1 A2 UART_CSA# UART_CSB# IOR# IOW# D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CSA# CSB# D0 D1 D2 D3 D4 D5 D6 D7 IOR# IOW# UART Channel A UART Channel B UART_INTB UART_INTA INTB INTA UART_RESET RESET RS-232 Serial Interface RS-232 Serial Interface |
Numéro de pièce similaire - ST16C2450 |
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Description similaire - ST16C2450 |
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