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KMM366S403CTL-G0 Fiches technique(PDF) 10 Page - Samsung semiconductor |
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KMM366S403CTL-G0 Fiches technique(HTML) 10 Page - Samsung semiconductor |
10 / 11 page PC66 SDRAM MODULE KMM366S403CTL REV. 3 Mar. '98 SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA0 A10/AP A9 ~ A0 Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H L L L H X X 3 Self refresh Entry L 3 Exit L H L H H H X X 3 H X X X 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable H X L H L H X V L Column address (A0 ~ A8) 4 Auto precharge enable H 4,5 Write & column address Auto precharge disable H X L H L L X V L Column address (A0 ~ A8) 4 Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Bank selection H X L L H L X V L X Both banks X H Clock suspend or active power down Entry H L H X X X X X L V V V Exit L H X X X X X Precharge power down mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H V X 7 No operation command H X H X X X X X L H H H 1. OP Code : Operand code A0 ~ A10/AP, BA0 : Program keys. (@ MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA0 : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA0 is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes : X |
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Description similaire - KMM366S403CTL-G0 |
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