Moteur de recherche de fiches techniques de composants électroniques |
|
TL16C2552IFN Fiches technique(PDF) 3 Page - Texas Instruments |
|
|
TL16C2552IFN Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 34 page www.ti.com TL16C2552 Block Diagram Crystal OSC Buffer Data Bus Interface A2 − A0 D7 − D0 CS CHSEL IOR IOW INTA INTB TXRDYA TXRDYB MFA MFB RESET XTAL1 XTAL2 BAUD Rate Gen 16 Byte Tx FIFO 16 Byte Rx FIFO Tx Rx UART Channel A BAUD Rate Gen 16 Byte Tx FIFO 16 Byte Rx FIFO Tx Rx UART Channel B CTSA DTRA DSRA, RIA, CDA RTSA CTSB DTRB DSRB, RIB, CDB RTSB VCC GND TXA RXA TXB RXB UART Regs UART Regs DEVICE INFORMATION TL16C2552 SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 A. MF output allows selection of OP, BAUDOUT, or RXRDY per channel. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME FN NO. RHB NO. A0 10 3 I Address 0 select bit. Internal registers address selection A1 14 6 I Address 1 select bit. Internal registers address selection A2 15 7 I Address 2 select bit. Internal registers address selection Carrier detect (active low). These inputs are associated with individual UART channels A and CDA, CDB 42, 30 – I B. A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate CHSEL 16 8 I function register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS is low. It is especially useful during the initialization routine. UART chip select (active low). This pin selects channel A or B in accordance with the state of CS 18 10 I the CHSEL pin. This allows data to be transferred between the user CPU and the 2552. Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit CTSA, 40, 28 25, 17 I data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the CTSB transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. 3 Submit Documentation Feedback |
Numéro de pièce similaire - TL16C2552IFN |
|
Description similaire - TL16C2552IFN |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |