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SN74CB3Q6800PW Fiches technique(PDF) 7 Page - Texas Instruments |
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SN74CB3Q6800PW Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 17 page www.ti.com PARAMETER MEASUREMENT INFORMATION VOH VOL CL (see Note A) TEST CIRCUIT S1 2 × VCC Open GND RL RL tPLH tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ VCC 0 V VOH VOL 0 V VOL + V∆ VOH − V∆ 0 V Output Control (VIN) VCC VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Output NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. 50 Ω VG1 VCC DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RL S1 V∆ CL 2.5 V ± 0.2 V 3.3 V ± 0.3 V VCC VI tPHZ/tPZH tPLZ/tPZL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 2 × VCC 2 × VCC GND GND 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω VCC or GND VCC or GND GND GND VCC VCC 30 pF 50 pF 30 pF 50 pF 30 pF 50 pF 0.15 V 0.3 V 0.15 V 0.3 V Output Control (VIN) Input Generator Input Generator VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VO SN74CB3Q6800 10-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS142A – OCTOBER 2003 – REVISED MARCH 2005 Figure 3. Test Circuit and Voltage Waveforms 7 |
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