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SN74AUP1G08IDCKRQ1 Fiches technique(PDF) 1 Page - Texas Instruments |
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SN74AUP1G08IDCKRQ1 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 15 page 1 B 2 GND 3 5 V CC 4 Y DCK PACKAGE (TOP VIEW) A SN74AUP1G08-Q1 www.ti.com SCES847 – DECEMBER 2012 Low-Power Single 2-Input Positive-AND Gate Check for Samples: SN74AUP1G08-Q1 1 FEATURES • Wide Operating VCC Range of 0.8 V to 3.6 V • Optimized for 3.3-V Operation 2 • AEC-Q100 Qualified with the Following Results: • 3.6-V Input/Output (I/O) Tolerant to Support Mixed-Mode Signal Operation – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature • tpd = 4.3 ns Max at 3.3 V Range • Suitable for Point-to-Point Applications – Device HBM ESD Classification Level H2 • Latch-Up Performance Exceeds 100 mA Per – Device CDM ESD Classification Level C3B JESD-78, Class II • Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption: ICC = 0.9 μA Max • Low Dynamic-Power Consumption: Cpd = 4.3 pF Typ at 3.3 V • Low Input Capacitance: Ci = 1.5 pF Typ • Low Noise: Overshoot and Undershoot < 10% of VCC • Ioff Supports Partial-Power-Down Mode Operation • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV, Typ at 3.3 V) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 NanoStar is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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