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G1-200P-85-1.6 Fiches technique(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce G1-200P-85-1.6
Description  Processor Series Low Power Integrated x86 Solution
Download  247 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

G1-200P-85-1.6 Fiches technique(HTML) 6 Page - National Semiconductor (TI)

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Revision 1.0
Table of Contents (Continued)
4.0
Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.1
INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . .... ... ... ... .... 97
4.1.1
Graphics Control Register . . . . . . . . . . . . . . . .... ... ... ... .... ... ... ... .... 97
4.1.2
Control Registers ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... 99
4.1.3
Graphics Memory . . . . . . .... ... ... ... ... .... ... ... ... .... ... ... ... .... 99
4.1.4
ScratchpadRAM ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 100
4.1.4.1
Initializationof Scratchpad RAM. . . . ... ... ... ... .. ... ... ... ... .. ... ... .. 100
4.1.4.2
ScratchpadRAM Utilization . . ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 100
4.1.4.3
BLT Buffer .. .. ... ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 100
4.1.5
Display Driver Instructions ... ... ... ... ... .... ... ... ... .... ... ... ... ... 102
4.1.6
CPU_READ/CPU_WRITE Instructions . . ... .... ... ... ... .... ... ... ... ... 102
4.2
INTERNAL BUS INTERFACE UNIT ... ... ... ... ... .... ... ... ... .... ... ... ... ... 103
4.2.1
FPU Error Support .. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 103
4.2.2
A20M Support . . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 103
4.2.3
SMI Generation . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 103
4.2.4
640 KB to 1MBRegion . .... ... ... ... ... .... ... ... ... .... ... ... ... ... 103
4.2.5
Internal Bus Interface Unit Registers . ... ... .... ... ... ... .... ... ... ... ... 104
4.3
MEMORYCONTROLLER ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 107
4.3.1
Memory Array Configuration . ... ... ... ... .... ... ... ... .... ... ... ... ... 108
4.3.2
Memory Organizations .. .... ... ... ... ... .... ... ... ... .... ... ... ... ... 109
4.3.3
SDRAM Commands . ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 110
4.3.3.1
SDRAM Initialization Sequence .. .. ... ... ... ... .. ... ... ... ... .. ... ... .. 111
4.3.4
Memory Controller Register Description . ... .... ... ... ... .... ... ... ... ... 112
4.3.5
Address Translation . ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 117
4.3.5.1
HighOrder Interleaving .. ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 117
4.3.5.2
Auto Low OrderInterleaving . . ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 117
4.3.5.3
Physical Address to DRAM Address Conversion ... .. ... ... ... ... .. ... ... .. 117
4.3.6
Memory Cycles . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 120
4.3.7
SDRAM InterfaceClocking ... ... ... ... ... .... ... ... ... .... ... ... ... ... 123
4.4
GRAPHICS PIPELINE ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 125
4.4.1
BitBLT/Vector Engine ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 125
4.4.2
Master/SlaveRegisters . .... ... ... ... ... .... ... ... ... .... ... ... ... ... 126
4.4.3
Pattern Generation .. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 126
4.4.3.1
MonochromePatterns ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 127
4.4.3.2
Dither Patterns ... ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 127
4.4.3.3
Color Patterns. ... ... ... ... ... .. ... ... ... ... .. ... ... ... ... .. ... ... .. 128
4.4.4
Source Expansion .. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 128
4.4.5
Raster Operations .. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... 128
4.4.6
Graphics Pipeline Register Descriptions . . . . .... ... ... ... .... ... ... ... ... 129


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