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74F632VC Fiches technique(PDF) 3 Page - National Semiconductor (TI) |
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74F632VC Fiches technique(HTML) 3 Page - National Semiconductor (TI) |
3 / 14 page Connection Diagram (Continued) Pin Assignment for Side Brazed DIP TLF9579 – 2 Order Number DP8406D (74F632DC) See NS Package Number D52A Functional Description MEMORY WRITE CYCLE DETAILS During a memory write cycle the check bits (CB0 through CB6) are generated internally in the EDAC by seven 16-in- put parity generators using the 32-bit data word as defined in Table II These seven check bits are stored in memory along with the original 32-bit data word This 32-bit word will later be used in the memory read cycle for error detection and correction ERROR DETECTION AND CORRECTION DETAILS During a memory read cycle the 7-bit check word is re- trieved along with the actual data In order to be able to determine whether the data from memory is acceptable to use as presented to the bus the error flags must be tested to determine if they are at the HIGH level The first case in Table III represents the normal no-error conditions The EDAC presents HIGHs on both flags The next two cases of single-bit errors give a HIGH on MERR and a LOW on ERR which is the signal for a correctable error and the EDAC should be sent through the correction cycle The last three cases of double-bit errors will cause the EDAC to signal LOWs on both ERR and MERR which is the interrupt indication for the CPU Error detection is accomplished as the 7-bit check word and the 32-bit data word from memory are applied to internal parity generatorscheckers If the parity of all seven group- ings of data and check bits is correct it is assumed that no error has occurred and both error flags will be HIGH TABLE I Write Control Function Memory EDAC Control DB Control DB Output CB Error Flags Cycle Function S1 S0 Data IO OEBn Latch Check IO Control ERR MERR LEDBO OECB Write Generate L L Input H X Output LH H Check Word Check Bit See Table II for details of check bit generation 3 |
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