DES Outputs

(RGB, VS, HS, DE)

~2MCcyc

PE Pulse High if

error is detected

0V

DES PCLK

Output

DES PE

Output

~1MCcyc

0V

0V

LM2506

SNLS186B – AUGUST 2006 – REVISED MAY 2013

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Parity Error Output

Parity Status is output as a pulse on the Parity Error (PE) output pin (DES) whenever there is a parity error.

These pulses could be counted or used by various diagnostic equipment. PE is a high going pulse that is 3 MC

cycles long for each frame containing an error. The PCLK output can be used to sample the PE bit. SET time is

nominally 2 MC cycles and a HOLD time of 1 MC cycle. The serial PE bit is Odd Parity and is based on the

RGB, and Control (VS, HS, DE) bits only. See Figure 10.

Figure 10. PE Output Timing

SYNCHRONIZATION DETECT AND RECOVERY

If a data error or clock slip error occurs over the MPL link, the LM2506 can detect this condition and recover from

it. The method chosen is a data transparent method, and has very little overhead because it does not use a data

expansion coding method. For the 18-bit color transaction (or frame), it uses two bits that are already required in

the 6-MC cycle transaction. Since double-edge clocking is used with two data signals, adding one clock cycle to

the transaction actually adds four bits. One of these bits is absolutely required - data enable - thus the others are

allocated to Parity and the frame sequence (F[1:0]). Therefore total overhead for each pixel is 3/24 or 12.5% in

18-bit RGB mode.

HOST SIDE FUNCTION

The LM2506 in serializer mode simply increments the two bit field F[1:0] on every pixel or frame transmitted.

Therefore every four frames, the pattern will repeat. It is very unlikely that this pattern would be found within the

payload data, and if it were found, the probability that it would repeat for many frames becomes infinitely small.

DISPLAY SIDE FUNCTION

The LM2506 in deserializer mode, upon a normal power up sequence, starts in the proper synchronization. It

looks for the incrementing pattern for N (N = 4 or 8) pixels (frames) and finding it, starts to output the pixel gray

scale data and timing signals.

If a random bit error occurs in the F[1:0] field, the hysteresis counter decrements by one, but the chip continues

to output data normally. The next frame will likely recover, incrementing the hysteresis counter back to the

maximum and things will continue normally. Likewise if a random bit error occurs in the gray scale data, it only

effects that bit and transmission will continue normally on the next frame (pixel). The worst case data bit error

would cause a one pixel wide glitch in the HS, VS or DE signals. This would likely cause a visible jump in the

display, but it would recover in a maximum of one display frame time. (typically under 20mS)

If however, a clock slip or error occurs, the next N frames will be bad and the F[1:0] field will not be detected

properly for each frame after the clock error. In this case, the hysteresis counter will decrement to zero quickly

(again where N=4 or 8 pixels). This action shuts down the output data (output PCLK held Low), and initiates a

search function for the incrementing sequence.

10

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