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LM2502 Fiches technique(PDF) 4 Page - Texas Instruments

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No de pièce LM2502
Description  Mobile Pixel Link Display Interface Serializer and Deserializer
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

LM2502 Fiches technique(HTML) 4 Page - Texas Instruments

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LM2502
SNLS176L – JANUARY 2004 – REVISED MAY 2013
www.ti.com
Table 2. Pad Assignment(1)
Pin #
Master
Slave
Ball #
Master
Slave
1
D0
D0
21
CLK
CLK
2
D3
D3
22
PD*
PD*
3
D7
D7
23
CS1*
CS1*
4
D6
D6
24
PLLCON2
PLLCON2
5
VSSIO
VSSIO
25
VSScore
VSScore
6
VDDIO
VDDIO
26
VDDcore
VDDcore
7
D8
D8
27
MF1
MF1
8
D9
D9
28
CS2*
CS2*
9
D10
D10
29
MD0M
MD1S
10
D11
D11
30
MODE
MODE
11
D13
D13
31
MC
MC
12
D14
D14
32
MD1M
MD0S
13
D12
D12
33
M/S*
M/S*
14
D15
D15
34
INTRM
CLKDIS*S
15
VSSIO
VSSIO
35
VSSA
VSSA
16
VDDIO
VDDIO
36
VDDA
VDDA
17
A/D
A/D
37
D2
D2
18
MF0
MF0
38
D5
D5
19
PLLCON0
PLLCON0
39
D1
D1
20
PLLCON1
PLLCON1
40
D4
D4
DAP
GND
GND
DAP
GND
GND
(1)
Note: Three pins are different between Master and Slave configurations.
Pin Descriptions
Description
No.
Pin Name
I/O, Type(1)
of Pins
Master (SER)
Slave (DES)
MPL SERIAL BUS PINS
MD[1:0]
2
IO, MPL
MPL Data Line Driver/Receiver
MPL Data Receiver/Line Driver
MC
1
IO, MPL
MPL Clock Line Driver
MPL Clock Receiver
VSSA
Ground
MPL Ground - see Power/Ground Pins
MPL Ground - see Power/Ground Pins
CONFIGURATION/PARALLEL BUS PINS
M/S*
1
I,
Master/Slave* Input,
Master/Slave* Input
LVCMOS
M/S* = H for Master
M/S* = L for Slave
PD*
1
I,
Power_Down* Input,
Power_Down* Input,
LVCMOS
H = Active
H = Active
L = Power Down Mode
L = Power Down Mode
MF0
1
IO,
Multi-function Input Zero (0):
Multi-function Output Zero (0):
(E or RD*)
LVCMOS
If MODE = L (m68 mode), E input pin, data is
If MODE = L (m68 mode),
latched on E High-to-Low transition or E may
E output pin, static High.
be static High and Data is latched on CS*
If MODE = H (i80 mode),
Low-to-High edge
Read Enable output pin, active Low.
If MODE = H (i80 mode), Read Enable input
pin, active low. Read data is driven when both
RD* and CS* are Low.
MF1
1
IO,
Multi-function Input One (1):
Multi-function Output One (1):
(R/W* or
LVCMOS
If Mode = L (m68 mode), Read/Write* pin,
If Mode = L (m68 mode)
WR*)
Read High, Write* Low
Read/Write* pin,
If Mode = H (i80 mode), Write* enable input
Read High, Write* Low
pin, active Low. Write data is latched on the
If Mode = H (i80 mode)
Low-to-High transition of either WR* or CS*
Write* enable output pin, active Low.
(which ever occurs first).
(1)
Note: I = Input, O = Output, IO = Input/Output, VDDIO ≤ VDD (VDDA = VDDcore). Do not float input pins.
4
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