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AD5660CRM-2 Fiches technique(PDF) 8 Page - Analog Devices

No de pièce AD5660CRM-2
Description  3 V/5 V, 16-Bit nanoDACTM D/A with 10 ppm/째C Max On-Chip Reference in SOT-23
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5660CRM-2 Fiches technique(HTML) 8 Page - Analog Devices

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AD5660
Preliminary Technical Data
Rev. PrJ Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled to GND.
2
VREFOUT
Reference Voltage Output.
3
VFB
Feedback connection for the output amplifier.
4
VOUT
Analog output voltage from DAC. The output amplifier has rail to rail operation.
5
SYNC
Level triggered control input (active low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge in which
case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
6
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
7
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
8
GND
Ground reference point for all circuitry on the part.


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