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AD5660BRJ-3 Fiches technique(PDF) 7 Page - Analog Devices

No de pièce AD5660BRJ-3
Description  3 V/5 V, 16-Bit nanoDACTM D/A with 10 ppm/째C Max On-Chip Reference in SOT-23
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5660BRJ-3 Fiches technique(HTML) 7 Page - Analog Devices

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Preliminary Technical Data
AD5660
Rev. PrJ | Page 7 of 20
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
Unit
Conditions/Comments
t1 1
50
33
ns min
SCLK Cycle Time
t2
13
13
ns min
SCLK High Time
t3
13
13
ns min
SCLK Low Time
t4
13
13
ns min
SYNC to SCLK Falling Edge Setup Time
t5
5
5
ns min
Data Setup Time
t6
4.5
4.5
ns min
Data Hold Time
t7
0
0
ns min
SCLK Falling Edge to SYNC Rising Edge
t8
50
33
ns min
Minimum SYNC High Time
t9
13
13
ns min
SYNC Rising Edge to SCLK Fall Ignore
t10
0
0
ns min
SCLK Falling Edge to SYNC Fall Ignore
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
Figure 2. Serial Write Operation


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