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AD7266ASU Fiches technique(PDF) 10 Page - Analog Devices |
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AD7266ASU Fiches technique(HTML) 10 Page - Analog Devices |
10 / 17 page AD7266 Preliminary Technical Data THEORY OF OPERATION CAPACITIVE DAC CAPACITIVE DAC CONTROL LOGIC COMPARATOR SW3 SW1 A A B B SW2 CS CS VIN+ VIN– VREF CIRCUIT INFORMATION The AD7266 is a fast, micropower, dual 12-bit, single supply, A/D converter that operates from a 2.7 V to 5.25 V supply. When operated from a 5 V supply, the AD7266 is capable of throughput rates of 2 MSPS when provided with a TBD MHz clock, and a throughput rate of 1.5 MSPS at 3 V. The AD7266 contains two on-chip differential track-and-hold amplifiers, two successive approximation A/D converters, and a serial interface with two separate data output pins, and is housed in a 32-lead LFCSP package, which offers the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part but also provides the clock source for each successive approximation ADC. The analog input range for the part can be selected to be a 0 V to VREF input or a 2 × VREF input with the analog inputs configured as either single ended or differential. The AD7266 has an on-chip 2.5 V reference that can be overdriven if an external reference is preferred. Figure 3. ADC Acquisition Phase When the ADC starts a conversion (Figure 4), SW3 opens and SW1 and SW2 move to position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribu- tion DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN– pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. The AD7266 also features power-down options to allow power saving between conversions. The power-down feature is implemented across the standard serial interface, as described in the Modes of Operation section. CONVERTER OPERATION The AD7266 has two successive approximation analog-to- digital converters, each based around two capacitive DACs. Figure 3 and Figure 4 show simplified schematics of one of these ADCs in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 3 (the acquisition phase), SW3, is closed, SW1 and SW2 are in position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. CAPACITIVE DAC CAPACITIVE DAC CONTROL LOGIC COMPARATOR SW3 SW1 A A B B SW2 CS CS VIN+ VIN– VREF Figure 4. ADC Conversion Phase Rev. PrG | Page 10 of 17 |
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