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CDC5801A Fiches technique(PDF) 3 Page - Texas Instruments

No de pièce CDC5801A
Description  Low Jitter Clock Multiplier
Download  18 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

CDC5801A Fiches technique(HTML) 3 Page - Texas Instruments

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CDC5801A
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE†
MODE
P0
P1
P2
CLKOUT/CLKOUTB
Multiplication with programmable
delay and phase alignment active‡
0
0
0
REFCLK multiplied by ratio per Table 1 selected by MULT/DIV terminals. Outputs
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
Division with programmable delay
and phase alignment active ‡
0
0
1
REFCLK divided by ratio per Table 2 selected by MULT/DIV terminals. Outputs
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
Multiplication only mode (phase
aligner bypassed) §
1
0
0
In this mode one can only multiply as per Table 1. Programmable delay capability
and divider capability is deactivated. PLL is running.
Test mode
1
1
0
PLL and phase aligner both bypassed. REFCLK is directly channeled to output.
Hi-Z mode
0
1
X
Hi-Z
† X = don’t care, Hi-Z = high impedance
‡ Please see Table 4 and Table 5 for explanation for the programmability and phase alignment functions.
§ In this mode the DLYCTRL and LEADLAG terminals must be strapped high or low. Lowest possible jitter is achieved in this mode, but a delay
of 200 ps to 2 ns expected typically from REFCLK to CLKOUT depending on the output frequency.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CLKOUT
20
O
Output clock
CLKOUTB
18
O
Output clock (complement)
DLYCTRL
7
I
Every rising edge on this terminal delays/advances the CLKOUT/CLKOUTB signal by 1/384th of the
CLKOUT/CLKOUTB period. (e.g., for a 90 degree delay or advancement one needs to provide 96 rising
edges). See Table 4.
GND
5
GND for VDDREF and VDDPD
GNDO
17, 21
GND for clock output terminals (CLKOUT, CLKOUTB)
GNDP
4
GND for PLL
GNDPA
8
GND for phase aligner
LEADLAG
6
I
Decides if the output clock is delayed or advanced with respect to REFCLK. See Table 4.
MULT0/DIV0
15
I
PLL multiplier and divider select
MULT1/DIV1
14
I
PLL multiplier and divider select
NC
19
Not used
PWRDNB
12
I
Active low power down state, CLKOUT/CLKOUTB goes low
P0
24
I
Mode control, see the Function Table
P1
23
I
Mode control, see the Function Table
P2
13
I
Mode control, see the Function Table
REFCLK
2
I
Reference input clock
STOPB
11
I
Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as per Table 3
VDDPA
9
I
Supply voltage for phase aligner
VDDPD
10
I
Reference voltage for the DLYCTRL, LEADLAG terminals and STOPB function
VDDREF
1
I
Reference voltage for REFCLK
VDDO
16, 22
I
Supply voltage for the output terminals (CLKOUT, CLKOUTB)
VDDP
3
I
Supply voltage for PLL


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