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ABSOLUTE MAXIMUM RATINGS

CDC2586

SCAS337D – FEBRUARY 1993 – REVISED APRIL 2004

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Clock input. CLKIN is the clock signal to be distributed by the CDC2586 clock-driver circuit. CLKIN

provides the reference signal to the integrated PLL that generates the clock output signals. CLKIN must

CLKIN

45

I

have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered

up and a valid CLKIN signal is applied, a stabilization time is required for the PLL to phase lock the

feedback signal to its reference signal.

CLR

40

I

CLR is used for testing purposes only.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one

FBIN

48

I

of the 12 clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks

to obtain zero phase delay between FBIN and CLKIN.

Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When

OE is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken

OE

42

I

directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop;

therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is

required before the PLL obtains phase lock.

Output configuration select. SEL0 and SEL1 select the output configuration for each output bank (e.g.,

SEL1, SEL0

51, 50

I

1/2

×, 1×, or 2×) (see Table 1 and Table 2).

TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all

TEST

41

I

outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that

bypasses the PLL circuitry. TEST should be strapped to GND for normal operation.

Output ports. These outputs are configured by the select inputs (SEL1, SEL0) to transmit one-half or

one-fourth the frequency of the VCO. The relationship between the CLKIN frequency and the output

1Y1-1Y3

2, 5, 8 12,

frequency is dependent on the select inputs and the frequency of the output being fed back to FBIN

2Y1-2Y3

15, 18 22,

O

(see Table 1 and Table 2). The duty cycle of the Y output signals is nominally 50%, independent of the

3Y1-3Y3

25, 28

duty cycle of CLKIN. Each output has an internal series resistor to dampen transmission-line effects

and improve the signal integrity at the load.

Output ports. 4Y1-4Y3 transmit one-half the frequency of the VCO regardless of the state of the select

inputs. The relationship between the CLKIN frequency and the output frequency is dependent on the

4Y1-4Y3

32, 35, 38

O

frequency of the output being fed back to FBIN (see Table 1 and Table 2). The duty cycle of the Y

output signals is nominally 50%, independent of the duty cycle of CLKIN. Each output has an internal

series resistor to dampen transmission-line effects and improve the signal integrity at the load.

UNIT

-0.5 V to 4.6 V

(2)

-0.5 V to 7 V

(2)

-0.5 V to 5.5 V

24 mA

-20 mA

-50 mA

(3)

1.2 W

-65

°C to 150°C

(1)

Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

The maximum package power dissipation is calculated using a junction temperature of 150

°C and a board trace length of 75 mils. For

more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book,

literature number SCBD002.

5