Moteur de recherche de fiches techniques de composants électroniques |
|
CDC925DLG4 Fiches technique(PDF) 10 Page - Texas Instruments |
|
CDC925DLG4 Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 19 page CDC925 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS633 – JULY 28, 1999 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0°C to 85°C (continued) CPUx PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 CPUx f(CPU) = 100 or 133MHz 6 10 ns tdis1 Output disable time SEL133/100 CPUx f(CPU) = 100 or 133MHz 8 10 ns t CPU clock period† f(CPU) = 100 MHz 10 10.04 10.2 ns tc CPU clock period† f(CPU) = 133 MHz 7.5 7.53 7.7 ns Cycle to cycle jitter f(CPU) = 100 or 133MHz 250 ps Duty cycle f(CPU) = 100 or 133MHz 45 55 % tsk(o) CPU bus skew CPUx CPUx f(CPU) = 100 or 133MHz 50 175 ps tsk(p) CPU pulse skew CPUn CPUn f(CPU) = 100 or 133MHz 2.2 ns t(off) CPU clock to APIC clock offset, rising edge 1.5 2.8 4 ns t(off) CPU clock to 3V66 clock offset, rising edge 0 0.75 1.5 ns t 1 Pulse duration width high f(CPU) = 100 MHz 2.6 4.3 ns tw1 Pulse duration width, high f(CPU) = 133 MHz 1.4 3.7 ns t 2 Pulse duration width low f(CPU) = 100 MHz 2.8 4.3 ns tw2 Pulse duration width, low f(CPU) = 133 MHz 1.7 4 ns tr Rise time VO = 0.4 V to 2.0 V 0.4 1.5 2.2 ns tf Fall time VO = 0.4 V to 2.0 V 0.4 1.4 2 ns † The average over any 1- µs period of time is greater than the minimum specified period. CPU_DIV2x PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT ten1 Output enable time SEL133/100 CPU_DIV2x f(CPU) = 100 or 133MHz 6 10 ns tdis1 Output disable time SEL133/100 CPU_DIV2x f(CPU) = 100 or 133MHz 8 10 ns t CPU DIV2 clock period† f(CPU) = 100 MHz 20 20.08 20.4 ns tc CPU_DIV2 clock period† f(CPU) = 133 MHz 15 15.06 15.3 ns Cycle to cycle jitter f(CPU) = 100 or 133MHz 250 ps Duty cycle f(CPU) = 100 or 133MHz 45 55 % tsk(o) CPU_DIV2 bus skew CPU_DIV2x CPU_DIV2x f(CPU) = 100 or 133MHz 50 175 ps tsk(p) CPU_DIV2 pulse skew CPU_DIV2n CPU_DIV2n f(CPU) = 100 or 133MHz 1.6 ns t 1 Pulse duration width high f(CPU) = 100 MHz 7.1 ns tw1 Pulse duration width, high f(CPU) = 133 MHz 4.7 ns t 2 Pulse duration width low f(CPU) = 100 MHz 7.3 8.9 ns tw2 Pulse duration width, low f(CPU) = 133 MHz 5 6.6 ns tr Rise time VO = 0.4 V to 2.0 V 0.4 1.4 2 ns tf Fall time VO = 0.4 V to 2.0 V 0.4 1.3 1.8 ns † The average over any 1- µs period of time is greater than the minimum specified period. |
Numéro de pièce similaire - CDC925DLG4 |
|
Description similaire - CDC925DLG4 |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |