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74LVC2G06 Fiches technique(PDF) 2 Page - NXP Semiconductors

No de pièce 74LVC2G06
Description  Inverters with open-drain outputs
Download  14 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC2G06 Fiches technique(HTML) 2 Page - NXP Semiconductors

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2004 Sep 10
2
Philips Semiconductors
Product specification
Inverters with open-drain outputs
74LVC2G06
FEATURES
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant input/output for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
•−24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and
−40 °C to +125 °C.
DESCRIPTION
The 74LVC2G06 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This
feature allows the use of this device in a mixed
3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant
for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G06 provides two inverting buffers.
The output of this device is an open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPLZ/tPZL
propagation delay input nA to output nY
VCC = 1.8 V; CL = 30 pF; RL =1kΩ
3.2
ns
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
2.0
ns
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
2.6
ns
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
2.3
ns
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω
1.6
ns
CI
input capacitance
2.5
pF
CPD
power dissipation capacitance per gate
VCC = 3.3 V; notes 1 and 2
5.9
pF


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