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74AHC1G126MDCKTEP Fiches technique(PDF) 2 Page - Texas Instruments

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No de pièce 74AHC1G126MDCKTEP
Description  SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

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SN74AHC1G126-EP
SCLS731 – DECEMBER 2013
www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
ABSOLUTE MAXIMUM RATINGS
(1)
over operating junction temperature range (unless otherwise noted)
VCC
Supply voltage range
−0.5 V to 7 V
VI
Input voltage range(2)
−0.5 V to 7 V
VO
Output voltage range(2)
−0.5 V to VCC + 0.5 V
IIK
Input clamp current
VI < 0
-20 mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20 mA
IO
Continuous output current
VO = 0 to VCC
±25 mA
Continuous current through VCC or GND
±50 mA
TJ
Junction temperature range
−55°C to 150°C
Tstg
Storage temperature range
−65°C to 150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
THERMAL INFORMATION
SN74AHC1G126-EP
THERMAL METRIC(1)
DCK
UNITS
5 PINS
θJA
Junction-to-ambient thermal resistance(2)
282.8
θJCtop
Junction-to-case (top) thermal resistance(3)
91.1
θJB
Junction-to-board thermal resistance(4)
60.1
°C/W
ψJT
Junction-to-top characterization parameter(5)
1.6
ψJB
Junction-to-board characterization parameter(6)
59.2
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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