74AC11620

OCTAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS062A − JULY 1987 − REVISED APRIL 1993

Copyright

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Layout

Minimize High-Speed Switching Noise

CMOS) 1-

µm Process

125

°C

Small-Outline Packages, and Standard

Plastic 300-mil DIPs

description

This octal bus transceiver is designed for

asynchronous

communication

between

data

buses. The control function implementation allows

for maximum flexibility in timing.

These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the

level at the output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device

so that the buses are effectively isolated.

The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of

OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control

inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of

bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be

complementary for the 74AC11620.

The 74AC11620 is characterized for operation from − 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OPERATION

OEBA

OEAB

OPERATION

L

L

B data to A bus

H

HA data to B bus

H

L

Isolation

L

H

B data to A bus,

A data to B bus

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

DW OR NT PACKAGE

(TOP VIEW)

1

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4

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8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

A1

A2

A3

A4

GND

GND

GND

GND

A5

A6

A7

A8

OEAB

B1

B2

B3

B4

B5

B6

B7

B8

OEBA

EPIC is a trademark of Texas Instruments Incorporated.