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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ADC08B200 Fiches technique(PDF) 3 Page - Texas Instruments |
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ADC08B200 Fiches technique(HTML) 3 Page - Texas Instruments |
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3 / 39 page  VD GND GND 3 9 10 VA GND 6 VA ADC08B200 www.ti.com SNAS388F – MARCH 2007 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description 6 VIN Analog signal input. Conversion range is VRB to VRT. Analog Input that is the high (top) side of the reference ladder of the ADC. Voltage on VRT and VRB inputs define the VIN 3 VRT conversion range. VRT should be more positive than VRB. Bypass well. Analog input that is the mid-point of the reference ladder. This 9 VRM pin should be bypassed to a quiet point in the ground plane with a 0.1 µF capacitor. DO NOT LOAD this pin. Analog Input that is the low side (bottom) of the reference 10 VRB ladder of the ADC. The voltages on VRT and VRB inputs define the VIN conversion range. Bypass well. Chip Power Down input. When this pin is high, the entire chip 13 PD is in the Power Down mode. Any data in the capture buffer is lost and the output pins hold the last byte that was output. ADC Power Down Input. When this pin is high, the ADC is 41 PDADC powered down. The capture buffer is active and the data within it may be clocked out. CMOS/TTL compatible digital clock Input. When the PLL is bypassed, the clock signal at this pin is the ADC sampling clock and VIN is sampled on the rising edge of this clock input. 46 CLK When the PLL is enabled, the signal at this input is the reference clock, which is multiplied to provide a higher frequency sample clock. Buffer Read Clock input. When the capture buffer is enabled, this input signal is used to read the data from the internal 19 RCLK buffer. The data output and the buffer empty flag (EF) transition with the rise of this clock. Write Enable input. A high level at this input causes a byte of 17 WEN data to be written into the capture buffer with the rise of each sample clock. Read Enable input. A high level at this input causes a byte of data to be read from the capture buffer with the rise of each 20 REN RCLK input. This rise of the REN input should be synchronous with the RCLK input and should not be high while the WEN input is high. Device Reset Input. A high level at this input resets all control 22 RESET logic on the chip. Output Enable input. A high level at this input enables the 37 OE output buffers. A low level at this input puts the digital data output pins into a high impedance state. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC08B200 |
Numéro de pièce similaire - ADC08B200 |
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Description similaire - ADC08B200 |
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