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ADC10080 Fiches technique(PDF) 8 Page - Texas Instruments

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No de pièce ADC10080
Description  78.6 mW A/D Converter
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

ADC10080 Fiches technique(HTML) 8 Page - Texas Instruments

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ADC10080
SNAS177H – JULY 2003 – REVISED MARCH 2013
www.ti.com
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 80 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for
TA = TMIN to TMAX: all other limits TA = 25°C
(1) (2) (3) (4)
Min
Typ
Max
Symbol
Parameter
Conditions
Units
(4)
(4)
(4)
CLK, DF, STBY, SENSE
fCLK1
Maximum Clock Frequency
80
MHz (min)
fCLK2
Minimum Clock Frequency
20
MHz
tCH
Clock High Time
6.25
ns
tCL
Clock Low Time
6.25
ns
Conversion Latency
6
Cycles
T = 25°C
2
3.5
5
ns
Data Output Delay after a Rising Clock
tOD
Edge
1
6
ns
tAD
Aperture Delay
1
ns
tAJ
Aperture Jitter
2
ps (RMS)
Differential VIN step from ±3V
Over Range Recovery Time
to 0V to get accurate
1
Clock Cycle
conversion
tSTBY
Standby Mode Exit Cycle
20
Cycles
(1)
To ensure accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(2)
With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV.
(3)
Typical figures are at TA = TJ = 25°C and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
(4)
Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge.
Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the ADC clock input signal.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and states that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:
Gain Error = Positive Full-Scale Error
− Negative Full-Scale Error
(1)
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale through positive full scale. The deviation of any given code from this straight line is
measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC10080 is ensured
not to have any missing codes.
NEGATIVE FULL SCALE ERROR is the difference between the input voltage (VIN+ − VIN) just causing a
8
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