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ADC08351 Fiches technique(PDF) 10 Page - Texas Instruments

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No de pièce ADC08351
Description  8-Bit, 42 MSPS, 40 mW A/D Converter
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

ADC08351 Fiches technique(HTML) 10 Page - Texas Instruments

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ADC08351
SNAS026E – JUNE 2000 – REVISED MARCH 2013
www.ti.com
Specification Definitions
ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz
plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input
signal is the full power bandwidth.
DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency
reconstructed sine wave at two different dc input levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave
at two different dc input levels.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD - 1.76)/6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100KHz
plus integer multiples of fCLK The input frequency at which the output is —3 dB relative to the low frequency input
signal is the full power bandwidth.
FULL SCALE OFFSET ERROR is the difference between the analog input voltage that just causes the output
code to transition to the full scale code (all 1's in the case of the ADC08351) and the ideal value of 1½ LSB
below the value of VREF.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
The end point test method is used.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and the availability
of that conversion result at the output. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
SAMPLING (APERTURE) DELAY is that time required after the fall of the clock input for the sampling switch to
open. The sample is effectively taken this amount of time after the fall of the clock input.
SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other
spectral components below one-half the sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to
the rms value of all of the other spectral components below half the clock frequency, including harmonics but
excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components to the
rms value of the input signal.
ZERO SCALE OFFSET ERROR is the difference between the analog input voltage that just causes the output
code to transition to the first code and the ideal value of ½ LSB for that transition.
10
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