200 2A

200 2A

1.6 V

To Output Pin

25 pF

ADC081S101

SNAS310D – JANUARY 2006 – REVISED JANUARY 2014

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ADC081S101 Timing Specifications

Symbol

Parameter

Conditions

Typical

Limits

Units

Minimum CS Pulse Width

10

ns (min)

CS to SCLK Setup Time

10

ns (min)

20

ns (max)

40

ns (max)

20

ns (max)

SCLK Low Pulse Width

ns (min)

SCLK High Pulse Width

ns (min)

7

ns (min)

SCLK to Data Valid Hold Time

5

ns (min)

25

ns (max)

6

ns (min)

25

ns (max)

5

ns (min)

Power-Up Time from Full Power-Down

1

µs

UP

(1)

Measured with the timing test circuit shown in Figure 2 and defined as the time taken by the output signal to cross 1.0V.

(2)

Measured with the timing test circuit shown in Figure 2 and defined as the time taken by the output signal to cross 1.0V or 2.0V.

(3)

time, independent of the bus loading.

Timing Diagrams

Figure 2. Timing Test Circuit

6

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