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QS5LV919 Fiches technique(PDF) 2 Page - Integrated Device Technology |
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QS5LV919 Fiches technique(HTML) 2 Page - Integrated Device Technology |
2 / 12 page 2 INDUSTRIALTEMPERATURERANGE QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN CONFIGURATION 20 19 18 15 16 23 22 24 21 17 VDD GND PLL_EN GND Q/2 Q3 LOCK VDD 2xQ Q1 25 28 27 26 VDD Q2 GND Q4 2 3 1 9 10 AVDD PE OE/RST SYNC0 FEEDBACK AGND 5 6 7 4 8 Q5 11 12 FREQ_SEL SYNC1 GND VDD REF_SEL 13 14 Q0 GND QSOP TOP VIEW PLCC TOP VIEW Q/2 GND Q3 VDD Q2 GND LOCK FEEDBACK REF_SEL SYNC0 AVDD PE AGND SYNC1 28 4 3 2 1 27 26 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ABSOLUTE MAXIMUM RATINGS (1) Symbol Rating Max. Unit VDD, AVDD SupplyVoltagetoGround –0.5 to +7 V DC Input Voltage VIN –0.5 to +5.5 V Maximum Power QSOP 655 mW Dissipation (TA = 85°C) PLCC 770 mW TSTG StorageTemperatureRange –65to+150 °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA=25°C,f=1MHz,VIN=0V) QSOP PLCC Parameter Typ. Max. Typ. Max. Unit CIN 3 446 pF |
Numéro de pièce similaire - QS5LV919 |
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Description similaire - QS5LV919 |
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