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LM181E06 Fiches technique(PDF) 10 Page - NXP Semiconductors |
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LM181E06 Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 26 page Product Specification 10 / 26 LM181E06 Liquid Crystal Display Ver 0.0 APR.07, 2002 3-3. Signal Timing Specifications This is the signal timing required at the input of the LVDS Transmitter. All of the interface signal timing should be satisfied with the following specifications for it’s proper operation. Notes: " No Variation of Hsync(DE) input is required for normal operation . "Input data shall be latched at the falling edge of DCLK. 1. Please refer transmitter data sheets for the detail timing condition (required setup, hold time and etc.) between video processor and LVDS transmitter. 2. Horizontal sync shall be active high. 3. Vertical sync shall be active high. 4. Data enable shall be active high. Table 6. TIMING TABLE ITEM SYMBOL MIN TYP MAX UNIT NOTES Dclk Period tCLK 18.18 18.52 18.87 ns 1 Frequency - 53.0 54.0 55.0 MHz Hsync Period tHP 784 844 904 tCLK 2 Width tWH 8 56 240 Vsync Period tVP 1034 1066 1098 tHP Frequency f V 59 60 61 3 Width tWV 2 3 24 Hz tHP DE (Data Enable) Horizontal Valid tHV 640 640 640 tCLK 4 Horizontal Back Porch tHBP 12 124 - Horizontal Front Porch tHFP 8 24 - Horizontal Blank - 144 - tHP- tHV Vertical Valid tVV Vertical Back Porch tVBP Vertical Front Porch tVFP Vertical Blank - 1024 1024 1024 tHP 1 38 - 1 1 - 10 - tVP- tVV Frequency f h 58.63 63.98 70.16 KHz |
Numéro de pièce similaire - LM181E06 |
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Description similaire - LM181E06 |
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