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FM24V02A-G Fiches technique(PDF) 6 Page - Cypress Semiconductor |
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FM24V02A-G Fiches technique(HTML) 6 Page - Cypress Semiconductor |
6 / 19 page FM24V02A Document Number: 001-90839 Rev. *G Page 6 of 19 High Speed Mode (Hs-mode) The FM24V02A supports a 3.4-MHz high-speed mode. A master code (00001XXXb) must be issued to place the device into the high-speed mode. Communication between master and slave will then be enabled for speeds up to 3.4-MHz. A STOP condition will exit Hs-mode. Single- and multiple-byte reads and writes are supported. Slave Device Address The first byte that the FM24V02A expects after a START condition is the slave address. As shown in Figure 7, the slave address contains the device type or slave ID, the device select address bits, and a bit that specifies if the transaction is a read or a write. Bits 7-4 are the device type (slave ID) and should be set to 1010b for the FM24V02A. These bits allow other function types to reside on the two-wire bus within an identical address range. Bits 3-1 are the device select address bits. They must match the corresponding value on the external address pins to select the device. Up to eight FM24V02A devices can reside on the same two-wire bus by assigning a different address to each. Bit 0 is the read/write bit (R/W). R/W = ‘1’ indicates a read operation and R/W = ‘0’ indicates a write operation. Addressing Overview After the FM24V02A (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The complete 15-bit address is latched internally. Each access causes the latched address value to be incremented automati- cally. The current address is the value that is held in the latch; either a newly written value or the address following the last access. The current address will be held for as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24V02A increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (7FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth S START Condition 9 8 2 1 Clock pulse for acknowledgement No Acknowledge Acknowledge DATA OUTPUT BY MASTER DATA OUTPUT BY SLAVE SCL FROM MASTER Figure 6. Data Transfer Format in Hs-mode handbook, full pagewidth F/S-mode Hs-mode F/S-mode 01 / A 1 DATA n (bytes +ack.) W / R S MASTER CODE S SLAVE ADD. Hs-mode continues S SLAVE ADD. P No Acknowledge Acknowledge or No Acknowledge Figure 7. Memory Slave Device Address handbook, halfpage R/W LSB MSB Slave ID 10 1 0 A2 A0 A1 Device Select |
Numéro de pièce similaire - FM24V02A-G |
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Description similaire - FM24V02A-G |
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