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MTV003N Fiches technique(PDF) 3 Page - List of Unclassifed Manufacturers

No de pièce MTV003N
Description  Microprocessor Compatible Monitor Controller
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MTV003N Fiches technique(HTML) 3 Page - List of Unclassifed Manufacturers

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MYSON
TECHNOLOGY
MTV003N
(MTV003)
MTV003 Revision 2.3 07/01/1998
3/13
Name
I/O
Pin#
Function
X2
O
8
Crystal 2. See X1. An appropriate capacitor to Ground, whose value
depends on the specified CLof the crystal, must be connected. For the
external clock source, this pin must be tied to Ground.
HS
I
9
Horizontal Sync. Horizontal synchronous signal input. The input level
is TTL compatible with internal 0.2V hysteresis. An internal 50K Ohm
pull-up resistor is connected to this pin.
VS
I
10
Vertical Sync. Vertical synchronous signal input. The input level is
TTL compatible with internal 0.2V hysteresis. An internal 50K Ohm
pull-up resistor is connected to this pin.
CMDB
I
11
Command Interface Enabler. A low active pin which must be forced
to low in excess of 16 cycles of DCK for 1 successful access of
command interface. It has an internal 50K Ohm pull-up resistor.
DCK
I
12
Command Interface Clock. This pin is used as the timing base for
command interface. The address or data portion for the serial in (out)
of DIO is recognized by counting the number of DCKs. It has an
internal 50K Ohm pull-up resistor.
DIO
I/O
13
Command Interface Data. This pin is a bidirectional pin. A
microprocessor can access any internal command registers through
the protocol of the address portion followed by the succeeding data
portion. It must complete 16 full DCK cycles for a valid access.
STOUT
O
14
Self-Test Video Output. (for self-test mode) This pin is the video
output pin of the self-test pattern generator. The generator enabler,
pattern modes, output band selection and output enabler are
programmed by Reg16.
XDA4
O
15
CMOS PWM D/A Converter 4. See DA0. The output pulse width can
be programmed by Reg30. It is a CMOS type output.
XDA3
O
16
CMOS PWM D/A Converter 3. See DA0. The output pulse width can
be programmed by Reg29. It is a CMOS type output.
XDA2
O
17
CMOS PWM D/A Converter 2. See DA0. The output pulse width can
be programmed by Reg28. It is a CMOS type output.
XDA1
O
18
CMOS PWM D/A Converter 1. See DA0. The output pulse width can
be programmed by Reg27. It is a CMOS type output.
XDA0
O
19
CMOS PWM D/A Converter 0. See DA0. The output pulse width can
be programmed by Reg26. It is a CMOS type output.
VDD
20
Positive Power Supply. +5 volts. 2 decoupling capacitors, 0.1 uF and
100 uF, must be connected to VDD and Ground as close to the device
as possible.
3.0 FUNCTIONAL DESCRIPTION
3.1 Crystal Oscillator and Clock Generator
The crystal oscillator shall be connected to an 8MHz(or 4MHz) crystal. X1, as shown in Fig.1, can be used as
an input source for the external clock or an output clock source to drive the external MCU. All timing
specifications are based on the frequency of X1 (or X1 divided by 2).
3.2 PWM D/A Converter
There are 2 types of D/A converters with 8-bit resolution: open-drain type (DA0 to DA2) and CMOS type (XDA0
to XDA4). The sampling frequency is 31.25KHz or 15.625KHz, depending on the use of the crystal. The
maximum external voltage applied is 12V for the open-drain type, and the output pulse width is programmable


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